For reducing electromagnetic interference from the operation of switch devices the rise and fall rates of turn-on and turn-off operations of the switch devices are controlled by means of a feedback control loop. Rise and fall rates of about 1 V/.mu.s are handled conventionally without serious problems. For applications having a pulsed operation, as in stepping motor drivers, etc., rise and fall rates of about 10 V/.mu.s to 30 V/.mu.s are more suitable. At such rise and fall rates, however, stability of the control loop is more critical. This is due to nonlinearities of the control loop together with a propagation delay in the driver stages, which contribute considerably to a total phase lag of the control loop.
For applications in switch devices which do not require a narrow definition of the rise and fall rate, the drain-to-gate capacitance of a MOS transistor is used. The gate drive is current-limited to a few microamperes. Such simple circuits depend greatly on the manufacturing spread of the gate capacitance of the MOS transistor. In addition, the turn-on delay and the turn-off delay are quite long since the gate voltage rises and falls slowly during turn-on and turn-off by reason of the relatively small gate capacitance of the MOS transistor, even in voltage ranges which are far removed from the turn-on threshold of the MOS transistor.
Such a conventional driver circuit is shown in FIG. 3. ON, VCC and VS designate an input terminal pin, a first voltage supply pin and a second voltage supply pin of an integrated circuit, respectively.
A pulsed switch control signal supplied to ON passes to a driver DR1 and from two outputs of the driver DR1 to two power sources IQ1 and IQ2. The power sources IQ1 and IQ2 deliver current I1 and I2, respectively, in a turned-on state and usually involve a push-pull stage whose two stages are driven in opposition by the driver DR1. A first node SK1 connected between the power sources IQ1 and IQ2 is connected to a gate of a switching transistor M1 in the form of an N-channel MOS transistor. A drain terminal D of the switching transistor M1 is connected to a load R.sub.L which is disposed in series with the switching transistor M1. Between the first node SK1 and a second node SK2 between the drain terminal D of the switching transistor M1 and the load R.sub.L is connected a capacitor C1 which represents the Miller capacitance of the drain-to-gate capacitance of the switching transistor M1. The current I1 charges the capacitor C1 and the gate of the switching transistor M1 and the current I2 discharges the capacitor C1 and the gate of the switching transistor M1.
The speed at which an output voltage can be switched at the second node SK2 is limited by the gate charging current or gate discharge current of the switching transistor M1.
The fall rate of a trailing edge of the output voltage at the drain terminal D of the switching transistor M1 is EQU dV/dt=-I1/C1 (1)
The rise rate of a leading edge of the output voltage at drain terminal D of the switching transistor M1 is EQU dV/dt=I2/C1 (2)
Typically I1 and I2 are selected to be equal in order to obtain the same rise and fall rates for both edges of a voltage pulse. Unfortunately the drain-to-gate capacitance of a MOS transistor depends greatly on its gate-to-drain voltage. A typical pulse response of a driver circuit according to FIG. 3 is shown in FIG. 4. In FIG. 4(a) a switch control pulse VIN supplied to the input terminal pin ON is shown, while in FIG. 4(b) a pulse response of the driver circuit shown in FIG. 3 is shown, in the form of the drain-to-source voltage Vds of the switching transistor M1.
The pulse response in FIG. 4(b) shows, firstly, a turn-off delay t1 and a turn-on delay t3 which come from the gate-to-source capacitance of the switching transistor M1. Two time periods t2 and t4 show a leading edge and a trailing edge of the pulse response, respectively. During the time periods t2 and t4 the slope rate or rate of change of the pulse response is not constant and is subject to manufacturing tolerances.
To obtain more precisely defined edges and reduce the delays (t1 and t3 in FIG. 4(b)) a control loop may be used. A conventional driver circuit with such a control loop is shown in FIG. 5. This circuit is quite similar to the circuit shown in FIG. 3. In addition to the circuit elements according to FIG. 3, the driver circuit shown in FIG. 5 has an amplifier AMP and a feedback capacitor C2. In this circuit, the slope rate is defined by the currents I1 (trailing edge) and I2 (leading edge) and the capacitor C2. The output of amplifier AMP is of sufficiently low resistance to charge and discharge the gate of the switching transistor M1, whereby the highest possible gate-to-drain capacitance C1 found in the operating range of the switching transistor M1 is assumed. The amplifier delivers so much output current that the capacitor C1 can be recharged much faster than the capacitor C2. This virtually eliminates the delay times t1 and t3 in FIG. 4(b). In addition, the feedback capacitor C2 can be well defined since it is less dependent on manufacturing spreads than the capacitor C1.
Considering a turn-on operation, the gate-to-source capacitance of the switching transistor M1 (not shown) is charged with the maximum current which the amplifier AMP can deliver. The turn-on delay (t3 in FIG. 4(b)) can therefore be reduced by orders of magnitude. When the gate-to-source voltage approaches the turn-on threshold voltage of the switching transistor M1, the drain voltage decreases, which leads to a discharge of the capacitor C2. After the switching transistor M1 is turned on, the on resistance of the switching transistor M1 decreases much faster than in the circuit shown in FIG. 3.
The driver circuit of FIG. 5 contains a complete control loop. The control loop must be designed so that it remains stable at the maximum gain of the amplifier AMP and for the maximum steepness of the switching transistor M1, which acts as a second amplifier stage together with the load R.sub.L. The steepness of the switching transistor M1 depends greatly on its operating point. The control loop gain increases with the load current (for inductive loads). For the control loop to remain stable, it must have enough phase latitude to maintain its stability even at the maximum working current of the switching transistor M1. At the same time, the control loop gain must be high enough to permit a suitable slope control for low load currents. Assuming a working current range of 100 mA to 1 A for the switching transistor M1 for example, the control loop gain changes by one order of magnitude.
With conventional methods, stability can be obtained for slope rates up to about 1 V/.mu.s. The dominant pole is usually defined by the gate capacitance of the switching transistor M1 together with the output impedance of driver amplifier AMP. For this stabilizing approach, the phase shift must be less than .pi./4 through the amplifier AMP at the highest frequency at which the control loop gain exceeds 1 (for an overshoot of 5%).